1. Field of Invention
The present invention relates to a method of forming a suicide, more particularly, to a method of forming Co silicide or salicide which provides an excellent p-type gate conductivity in dual gates consisting of fine grains for CMOS devices by increasing grain size in the p-type gate. The p-type gate is then re-doped with n-type impurities such as As or the like having a characteristic of increasing grain sizes within a critical dose, and which also reduces sheet resistance by securing thermal stability in following processing steps.
2. Discussion of Related Art
In an ultra highly integrated semiconductor device, the widths of impurity regions and gates are decreased. Thus, operation speed is reduced because contact resistance of the impurity region and sheet resistance of the gate are increased.
The contact and sheet resistances may be reduced by forming silicide layers on a gate electrode of doped polysilicon, or by forming electrodes of a semiconductor device with a low resistance substance such as Al alloy, W, or the like. In this case, another suicide layer may be formed on surfaces of the impurity regions as soon as the silicide layer is formed on the gate electrode of doped polysilicon. This is called a salicide structure which decreases contact resistance.
As mentioned above, the relatively high resistance of a gate is the major factor of reducing the operation speed of a semiconductor device because a design rule for a semiconductor device becomes more strict.
A line width or a critical dimension is scaled down to submicron range to improve operational characteristics and improve the degree of integration in semiconductor integrated circuits. This reduces spaces between adjacent gate lines of MOS transistors in the semiconductor integrated circuit. Naturally, parasitic capacitance among the gate lines increases greatly, thereby lowering the signal transferring speed of the circuit.
In such a semiconductor integrated circuit, the signal transferring speed is affected by a delay time, which depends on a line resistance R of a gate line and a parasitic capacitance C among gate lines.
Therefore, the line resistance or the parasitic capacitance is decreased by increasing an interval between the gate lines in order to improve the signal transferring speed of a circuit.
Unfortunately, it is hard to increase the degree of integration when increasing the spacing between the gate lines. Therefore, the delay time of a signal is instead reduced by decreasing the line resistance of the gate. In order to reduce the line resistance of the gate, a gate having a polycide structure is formed in which silicide is stacked on heavily doped polysilicon.
Fabricating a gate electrode having low resistance is essential to improve the operation speed of a device. For such improvement, a gate electrode of refractory metal silicide (with a low specific resistance) is fabricated. Such a gate electrode having has a polycide (silicide on doped polysilicon) structure.
Although WSi2 is frequently used in the polycide structure, some silicide having a lower resistance is required for the reduced area occupied by a unit device because of the increased integration of the device. Besides, the specific resistance of WSi2 is 60 to 200 xcexcxcexa9-cm. Therefore, CoSi2 or TiSi2 having a specific resistance of 15 to 20 xcexcxcexa9-cm meets this requirement.
Methods of forming a polycide structure may be divided into two categories. First, silicide may be formed by depositing a metal layer on a doped polysilicon and by reacting the metal with the doped polysilicon in a thermal treatment. In this case, the resultant polycide, which is relatively thick, fails to form a thick and uniform silicide layer.
Generally, the reaction between pure metal and silicon is very vigorous, creating a rough morphology at the interface between silicide and silicon. Therefore, it is hard to pattern a gate electrode precisely. This phenomenom is disclosed in detail in, for example, [J. S. Byun et al. J. Electrochem. Soc., vol. 144,3175(1997)].
Moreover, when fine-grained polysilicon is used to permit sufficient doping, the vigorous reaction between the doped polysilicon of which grain boundaries are much enhanced and the heavily-doping dopants fails to form an uniform polycide structure.
Second, there is a method forming polycide by depositing a silicide substance directly on a doped polysilicon, instead of reacting metal and silicon in a thermal treatment. Generally, a sputtering method is used to form a silicide layer on a doped polysilicon layer using a silicide composite target.
Unfortunately, this method lessens the reliability of a resultant semiconductor device due to particles generated from forming silicide as the integration degree of a device increases. Specifically, the sputtering rates of the respective elements in the composite target consisting of metal and silicon differ from each other, which prevents formation of a silicide layer having an uniform composition and causes the generation of particles.
As a CMOS transistor becomes highly integrated and sizes of NMOS and PMOS transistors are reduced accordingly, short channel effect and hot carriers ruin the characteristics of a device. Hence, the degradation of the NMOS and PMOS transistors is prevented by using an LDD(lightly doped drain) structure.
Gates of the NMOS and PMOS transistors of a CMOS device are heavily doped with n-type impurities commonly. Accordingly, a channel of the PMOS transistor is not formed in a top surface of a substrate but formed in a bulk of the substrate, thereby lowering breakdown voltage of the transistor due to punch through.
Therefore, a dual-gate CMOS transistor device is conventionally available in which a PMOS transistor has a heavily-doped gate doped with p-type impurities whereas the other gate of an NMOS transistor is heavily doped with n-type impurities. The channel of the PMOS transistor in such a dual-gate CMOS device is formed in a top surface of a substrate, thereby preventing the decrease of breakdown voltage due to punch-through.
The dual-gate CMOS transistor prevents a lowering of the signal transferring speed because of the increased integration of a device by reducing sheet resistance by forming a polycide gate structure consisting of heavily doped polysilicon and silicide.
Although very fine-grained polysilicon is required for doping a gate sufficiently because of scaling-down, thermal stability of silicide of CoSix or the like of such polysilicon constitution is very poor because of the grain sizes participating directly in the silicidation reaction with Co.
Namely, silicidation occurs abruptly since the total surface area of the polysilicon grains is increased. Abrupt silicidation causes metal agglomeration in a subsequent thermal treatment, thereby drastically increasing sheet resistance.
FIG. 1A to FIG. 1D illustrate a method of forming suicide in a semiconductor device, in particular cross-sectional views of a dual-gate CMOS transistor device according to a related art.
Referring to FIG. 1A, an n-well 11 and a p-well 12 are formed in predetermined portions of a semiconductor substrate 20 by doping the substrate selectively with n and p-type impurities, respectively.
A field oxide layer 13 electrically isolating unit devices is formed at a boundary between the n- and p-wells 11 and 12 by, for example, LOCOS (Local Oxidation of Silicon) or STI (shallow trench isolation). A gate insulating layer 14 is formed by thermally oxidizing surfaces of the n- and p-wells 11 and 12.
A silicon layer 15 is then formed on the field oxide layer 13 and the gate insulating layer 14 by depositing undoped polysilicon or amorphous silicon by chemical vapor deposition(hereinafter abbreviated CVD). If amorphous silicon is deposited, the amorphous silicon is transformed into polycrystalline silicon by a thermal treatment. In this case, the silicon layer 15 consisting of polycrystallites is made of fine grains to facilitate impurity doping to reduce gate resistance.
Referring to FIG. 1B, after the silicon layer 15 has been coated with photoresist, a first photoresist pattern 16 exposing a portion of the silicon layer 15 over the p-well 12 region is formed by carrying out exposure and development.
A first polysilicon layer 150 doped with n-type impurities is formed by carrying out ion-implantation with n-type impurities such as As or the like on the exposed portion of silicon layer 15 over p-well region 12 using the first photoresist pattern 16 as an ion-implanting mask. The doped first polysilicon layer 150 will be patterned to become a gate of an NMOS transistor.
Referring to FIG. 1C, the portion of silicon layer 15 over the n-well 11 region which is not doped is exposed by removing the first photoresist pattern 16 by O2 ashing or the like.
After the exposed undoped portion of silicon layer 15 and the doped first polysilicon layer 150 doped with n-type impurities have been coated with another photoresist, a second photoresist pattern 17 exposing the undoped portion of silicon 15 layer over the n-well 11 region is formed by carrying out exposure and development.
Then, a second polysilicon layer 151 doped with p-type impurities is formed by carrying out ion-implantation with p-type impurities such as B, BF2 or the like using the second photoresist pattern 17 as an ion-implanting mask. The doped second polysilicon layer 151 will be patterned to become a gate of an PMOS transistor.
Referring to FIG. 1D, the doped first polysilicon layer 150 formed over the p-well 12 region is exposed by removing the second photoresist pattern 17 by O2 ashing or the like.
From now on, the description will be continued with respect to two conventional embodiments, including a method of fabricating a CMOS device with gate electrodes that are formed with the polycide structure only, and a method of forming the salicide structure including silicide formed on impurity diffusion regions and on a gate electrode.
First, a method of fabricating a CMOS device having the salicide structure is explained in the following description.
An n-type gate 1500 consisting of polysilicon doped with n-type impurities and a p-type gate 1510 consisting of polysilicon doped with p-type impurities are formed by patterning the first polysilicon layer 150 doped with n-type impurities and the second polysilicon layer 151 doped with p-type impurities by photolithography, respectively. In this case, the oxide layer is also patterned to form first and second gate insulating layers 140 and 141 between the gates 1500 and 1510 and n-well 11 and p-well 12, respectively.
And, by using a general method of fabricating, a CMOS transistor device, gate sidewall spacers 18 and impurity diffusion regions 19 are formed corresponding to the n-type and p-type gates 1500 and 1510, respectively. In this case, the impurity diffusion regions 19 of the n-type gate 1500 are formed by doping an active region of the substrate with n-type impurity ions, while the other impurity diffusion regions 19 of the p-type gate 1510 are formed by doping the other active region with p-type impurity ions. Also, the impurity diffusion regions 19 may be formed to have LDD (lightly doped drain) structures.
A metal layer (not shown in the drawing) is formed over the substrate including a top surface of the exposed n-type gate 1500 of silicon and exposed surfaces of the impurity diffusion regions 19 by depositing Co, Ti or the like by sputtering for forming silicide. In this case, the metal layer is formed to a thickness corresponding to a desired height of the final polycide structure gate electrodes by being added to the height of each of the gates 1500 and 1510.
Silicide layers 20 and 21 for reducing electrode resistance are formed on the gates 1500 and 1510 and the impurity diffusion regions 19 to provide the final gate electrodes having the polycide structure by reacting the metal layer with silicon by carrying out rapid thermal annealing on the silicon and metal layers. In this case, the step of forming silicide layers on both the gate electrode and the impurity diffusion regions is called salicidation, thereby forming the salicide structure. The remaining metal layer not used in the salicidation process is removed.
Second, a method of fabricating a CMOS device having gates including the polycide structure is explained in the following description, which is continued successively after the steps in FIG. 1C.
After the doped first polysilicon layer 150 formed over the p-well 12 region has been exposed by removing the second photoresist pattern 17 by O2 ashing or the like, a metal layer is formed on the doped first and second polysilicon layers 150 and 151 by depositing refractory metal such as Co, Ti and the like.
A silicide layer is formed on the doped first and second polysilicon layers 150 and 151 by reacting silicon with the metal layer by carrying out thermal treatment such as annealing on the substrate.
Gates are formed by patterning predetermined portions of the silicide layer, the first and second polysilicon layers, and the gate insulating layers by photolithography.
Impurity diffusion regions are formed by implanting n-type impurities such as As, P, etc. in the p-well and p-type impurities such as B, BF2, etc. in the n-well using the gates as an implantation mask, respectively. The impurity diffusion regions may have LDD structures by adding gate sidewall spacers to sides of the respective gates.
As mentioned in the above explanation, when CoSix is formed by using fine-grained polysilicon consisting of a plurality of fine grains as a matrix under the design rule of 0.25 xcexcm, the morphology of the interface between the suicide layer and the fine-grained polysilicon layer is rough and nonuniform because silicidation occurs abruptly.
The non-uniformity causes agglomeration of the silicide layer (CoSix), thereby increasing sheet resistance. Therefore, it is difficult to use fine-grained polysilicon having excellent gate doping efficiency.
Namely, the gate doped with p-type impurities of which grain sizes has not been changed brings about metal agglomeration, thereby degrading characteristics of sheet resistance so as to become similar to that of undoped polysilicon. Hence, using polysilicon of fine grains for a gate has a benefit of increasing gate doping efficiency but it degrades thermal stability of the silicide.
Accordingly, the present invention is directed to a method of forming silicide that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to improve sheet resistance and thermal stability of silicide consisting of Co and the like by forming n-type and p-type polysilicon layers for forming dual-gates. Each of the polysilicon layers is doped with opposite conductivity type impurities and is formed by growing the grain size of the p-type polysilicon layer by additionally doping the p-type polysilicon layer only with n-type impurities such as As, etc. at a critical density of 1E19 to 5E20ions/cm3.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes forming an undoped polysilicon layer consisting of a plurality of grains, doping the polysilicon layer with p-type impurity ions, doping the doped polysilicon layer with ions that increase the grain sizes of the polysilicon layer by being heated, forming a metal layer for silicidation on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the polysilicon layer with the metal layer.
In another aspect, the present invention includes forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer consisting of a plurality of grains on the gate insulating layer, doping the polysilicon layer with p-type impurity ions, doping the doped polysilicon layer with ions for increasing the grain size of the polysilicon layer by being heated, forming a metal layer for silicidation on the twice doped polysilicon layer to a predetermined thickness, forming a silicon-metal compound layer by reacting a portion of the twice doped polysilicon layer with the metal layer, patterning the silicon-metal compound layer, the polysilicon layer remaining from forming the silicon-metal compound layer and the gate insulating layer to form a gate electrode pattern consisting of the remaining part of the silicon-metal compound layer, the polysilicon layer and the gate insulating layer, and forming a pair of impurity diffusion regions facing each other laterally under the gate electrode pattern in the semiconductor substrate and forming an insulating sidewall spacer at a side of the gate electrode pattern.
In another aspect, the present invention includes forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer consisting of a plurality of grains on the gate insulating layer, doping the polysilicon layer with p-type impurity ions, doping the doped polysilicon layer with ions for increasing grain sizes of the polysilicon layer by being heated, patterning the polysilicon layer and the gate insulating layer to form a gate electrode pattern consisting of the patterned polysilicon layer and the gate insulating layer, forming a pair of impurity diffusion regions facing each other laterally under the gate electrode pattern in the semiconductor substrate and forming an insulating sidewall spacer of insulator at a side of the gate pattern, forming a metal layer on the gate electrode pattern and the impurity diffusion regions to a predetermined thickness, and forming a metal-silicon compound layer and a metal-semiconductor compound layer by reacting the metal layer with a remaining portion of the polysilicon layer and the semiconductor substrate in the impurity diffusion regions, respectively.
In a further aspect, the present invention includes forming a p-well and an n-well separated by a device-isolating layer in predetermined portions of a semiconductor substrate, forming a gate insulating layer on the p- and n-wells, forming a first polysilicon layer doped with n-type impurities on the insulating layer over the p-well and forming a second polysilicon layer doped with p-type impurities on the insulating layer over the n-well, doping the second polysilicon layer with ions for increasing grain sizes of polysilicon by being heated, patterning the first and second polysilicon layers and the insulating layer to form first and second gate electrode patterns, forming a pair of impurity diffusion regions facing each other laterally under each of the first and second gate electrode patterns in the semiconductor substrate and forming an insulating sidewall spacer at a side of each of the first and second gate electrode patterns, respectively, thereby forming an NMOS transistor and a PMOS transistor in the p- and n-wells, respectively, forming a metal layer on the first and second gate electrode patterns and on the impurity diffusion regions to a predetermined thickness, forming a metal-silicon compound layer and a metal-semiconductor compound layer by reacting the metal layer with remaining portion of the first and second polysilicon layers and the semiconductor substrate in the impurity diffusion regions, respectively.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.